ASWIT PUNGSEMA; PRADONDET NILAGUPTA. Parallel Logic Synthesis Optimization for Digital Sequential Circuit. Agriculture and Natural Resources, Bangkok, Thailand, v. 36, n. 3, p. 319–326, 2002. Disponível em: https://li01.tci-thaijo.org/index.php/anres/article/view/242736. Acesso em: 27 aug. 2026.