The Effect of Temperature on Threshold Voltage, The Low Field Mobilty and the Series Parasitic Resistance of PMOSFET

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Published: Mar 30, 2018
Keywords:
NMOS, PMOS, Threshold voltage

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Nattaphon Sakuna
Faculty of Engineering, King Mongkut’s Institute of Technogy Lakrabang, Bangkok, Thailand
Rangson Muanghlua
Faculty of Engineering, King Mongkut’s Institute of Technogy Lakrabang, Bangkok, Thailand
Surasak Niemcharoen*
Mahanakorn University of Technology Bangkok, Thailand, National Electronics and Technology Center, Pathumtani, Thailan
Anucha Ruangphanit
National Electronics and Technology Center, Pathumtani, Thailand

Abstract

This article describes the effect of temperature on the threshold voltage, low field mobility and S/D series parasitic resistance of PMOS over operating temperature range of 27 0C to 125 0C. The relation of IDS and VGS in a linear region was used with a different of channel length at a fixed value of channel width that effect of the channel width is excluded. The extraction procedure is based on the measurement of the transconductance characteristics of MOSFET in the linear region. The results show that, the temperature coefficient for threshold voltage is around 1.7mV/0C approximately. The low field mobility degradation parameter is decreased by the factor of 0.68. The temperature coefficient of source-drain series resistance per unit channel width (RDSW) is approximately 16.7 ohm-um/K. These data are necessary for the circuit designer to understanding well in the elevated operating temperatures.


Keywords: NMOS, PMOS, Threshold voltage


Email: [email protected]

Article Details

Issue
Vol. 13 No. 1 (2013)
Section
Special Section

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