Parallel Logic Synthesis Optimization for Digital Sequential Circuit

Abstract

High-level synthesis tools are very important for designing electronic circuits. A lower level logic gates are synthesized by optimization of the circuit’s combination part, which is then realized by mapping on programmable devices such as FPGAs. This synthesis process is a computation intensive task. In this paper, we propose an alternative method to synthesis a sequential logic circuit which reduces time consuming in synthesis process. First using a parallel partitioning algorithm partition the whole circuit into sub-circuits and then using parallel sub-circuit synthesis in order to reduce computation. The LGSynth’91 benchmark suite used for experiment is in net-list format. Our result shows that the number of partition is increasing whereas the synthesis time is reduced as the number of processor is increased.