Half Flash 4-Bit (BCD) using New Current-Mode Algorithmic ADC

Abstract

This paper presents a current-mode technique for the design of algorithmic ADC in half-flash 4-bit (BCD). This circuit can be converted to 4-bit output at each moment and multiple output bit numbers by serial connection. It uses attenuation current quantization level for quality improvement by using the active current mirror which is better than the cascade current mirror. The advantages and disadvantages of different current mirror structures for using in the ADC in half-flash (BCD) are discussed. Experimental results for using a 0.13 μm CMOS process are reported, which is displayed capable to the slowest conversion time is less than 80 ns, 12.5 MHz, power consumption of 1 mw. input current of 0-100 μA and 2.5V single supply. Its feasibility agrees with simulation results of PSPICE program. From simulation testing, the conversion rate is faster than other method.